Intelligent IP for automated A/MS IC design and technology porting

What?

Automate your Analog Designs with Libraries

When?

07-01-2020 14.00 - 15.00 Uhr

Where?

Web-Seminar

Who?

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Learn how our solution on analog automation can support your IC design flow to meet tapeouts in time. Whether your design phase should be accelerated, design migration eased, or your custom problem be automated–with intelligent IPs, Fraunhofer IIS/EAS offers an applied solution for a new era of analog integrated circuit design.

Referent: Benjamin Prautsch

Webinar-Anmeldung